
JEDEC, a semiconductor component standard specification organization, announced the final specifications of DDR5, the next-generation DRAM standard, on July 14 (local time). It was originally scheduled to end development in 2018, but the plan was delayed for more than two years to respond to the growing demands of system manufacturers.
According to JEDEC, compared to the maximum memory density per die area, DDR4 is 16Gbits, while DDR5 is 64Gbits. In other words, in the case of UDIMM, the capacity per memory was 32GB for DDR4, but up to 128GB for DDR5. In the case of LDIMM, the maximum capacity reaches 2TB.
In addition, the data transfer rate per input/output pin is up to 3.2Gbps for DDR4, while DDR5 is 6.4Gbps in the 4.8Gbps specification at the time of commercialization. However, as DDR4 memory exceeding the official maximum of 3.2Gbps is emerging, it is estimated that DDR5 memory will also appear beyond the maximum specification.
Also, the fact that a single memory module is divided into two channels is a big change for DDR5. It does not have a 64-bit data channel per DDR5 memory module, but has an independent 32-bit data channel for each DIMM or a 40-bit data channel considering ECC. In addition, the burst length per channel was BL8 in DDR4, which was BL16, and the number of memory banks is 32 times. Therefore, the effective bandwidth of DDR5 is doubled compared to DDR4.
The operating voltage of DDR5 also went down, and from 1.2V in DDR4 to 1.1V in DDR5. In addition, DDR5 is equipped with a voltage regulator for memory only on the DIMM, not the motherboard. This change allows a simpler design of the motherboard and slightly reduces production costs. In addition, DDR5 has a fundamentally improved pin assignment, so the number of DDR5 pins is 288 pins the same as DDR4, but there is no compatibility.
JEDEC predicts that DDR5 memory for servers will appear in the market in 2021, and the life cycle is 7 years like DDR4.
Carolyn Duran, vice president of Intel’s Memory I/O division, said DDR5 has dramatically improved memory performance and achieved a 50% increase in bandwidth with new technologies for AI and high performance computing demand. Related information can be found here .
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